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19-2905; Rev 0; 8/03
12.5Gbps CML 2 x 2 Crosspoint Switch
General Description
The MAX3841 is a low-power, 12.5Gbps 2 x 2 crosspoint switch IC for high-speed serial data loopback, redundancy, and switching applications. The MAX3841 current-mode logic (CML) inputs and outputs have isolated VCC connections to enable DC-coupled interfaces to 1.8V, 2.5V, or 3.3V CML ICs. Fully differential signal paths and Maxim's second-generation SiGe technology provide optimum signal integrity, minimizing jitter, crosstalk, and signal skew. The MAX3841 is ideal for serial OC-192 and 10GbE optical module, line card, switch fabric, and similar applications. The MAX3841 has 150mVP-P minimum differential input sensitivity, and 500mVP-P nominal differential output swing. Unused outputs can be powered down individually to conserve power. In addition to functioning as a 2 x 2 switch, the MAX3841 can be configured as a 2:1 multiplexer, 1:2 buffer, or dual 1:1 buffer. The MAX3841 is available in a 4mm x 4mm 24-pin thin QFN package, and consumes only 215mW with both outputs enabled. o Up to 12.5Gbps Operation o Less Than 10psP-P Deterministic Jitter o Less Than 0.7psRMS Random Jitter o 1.8V, 2.5V, and 3.3V DC-Coupled CML I/O o Independent Output Power-Down o 4mm x 4mm Thin QFN Package o -40C to +85C Operation o +3.3V Core Supply o 215mW Power Consumption (Excluding Termination Currents)
Features
MAX3841
Applications
OC-192, 10GbE Switch/Line Cards OC-192, 10GbE Optical Modules System Redundancy/Self Test Clock Fanout
MAX3841ETG PART
Ordering Information
TEMP RANGE -40C to +85C PINPACKAGE 24 Thin QFN PKG. CODE T2444-1
Pin Configuration appears at end of data sheet.
Typical Application Circuit
1.8V 2.5V 3.3V 2.5V VCC1OUT SDI+ 10Gbps SERIAL OPTICAL MODULE SDISDO+ SDO2.5V VCC1IN SEL1 SEL2 ENO1 ENO2 VCC2OUT GND OUT1+ OUT1IN1+ IN1MAX3841 VCC VCC2IN IN2+ IN2OUT2+ OUT21.8V 3.3V 1.8V 10Gbps CDR/SERDES ASIC SDO+ SDOSDI+ SDI-
LOOPBACK
________________________________________________________________ Maxim Integrated Products
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12.5Gbps CML 2 x 2 Crosspoint Switch MAX3841
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +4.0V CML Supply Voltage (VCC_IN, VCC_OUT)...........-0.5V to +4.0V Continuous Output Current (OUT1, OUT2)...................25mA CML Input Voltage (IN1, IN2)...........-0.5V to (VCC_IN + 0.5V) LVCMOS Input Voltage (SEL1, SEL2, ENO1, ENO2) .........................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 24-Pin Thin QFN (derate 20.8mW/C above +85C).............................................................1352mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, VCC_IN = +1.71V to VCC, VCC_OUT = +1.71V to VCC, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCC_IN = VCC_OUT = 1.8V, TA = +25C, unless otherwise noted.)
PARAMETER Core Supply Current Data Rate CML Input Differential CML Input Common Mode CML Input Termination CML Input Return Loss CML Output Differential CML Output Termination CML Output Transition Time Deterministic Jitter Random Jitter Propagation Delay Channel-to-Channel Skew Output Duty-Cycle Skew LVCMOS Input Current LVCMOS Input High Voltage IIH, IIL VIH tR, tF VOUT VIN SYMBOL ICC (Note 1) AC-coupled or DC-coupled (Note 2) DC-coupled Single ended Up to 10GHz (Note 2) Single ended 20% to 80% (Notes 1, 3) (Notes 1, 4) VIN = 150mVP-P (Notes 1, 5) Any input to output (Note 1) (Note 1) 50% input duty cycle (Notes 1, 3) -10 1.7 0.3 100 400 42.5 CONDITIONS Excluding CML termination currents 0 150 VCC_IN - 0.3 42.5 50 12 500 50 600 57.5 30 10 0.7 140 12 8 +10 MIN TYP 65 MAX 90 12.5 1200 VCC_IN 57.5 UNITS mA Gbps mVP-P V dB mVP-P ps psP-P psRMS ps ps ps A V
Note 1: Note 2: Note 3: Note 4:
Guaranteed by design and characterization. Differential swing is defined as VIN = (IN_+) - (IN_-) and VOUT = (OUT_+) - (OUT_-). See Figure 1. Measured using a 0000011111 pattern at 12.5Gbps, and VIN = 400mVP-P differential. Measured at 9.953Gbps using a pattern of 100 ones, 27 - 1 PRBS, 100 zeros, 27 - 1 PRBS, and at 12.5Gbps using a K28.5 pattern. VCC_IN = VCC_OUT = 1.8V, and VIN = 400mVP-P differential. Note 5: Refer to Maxim application note HFAN-04.5.1: Measuring Random Jitter on a Digital Sampling Oscilloscope.
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12.5Gbps CML 2 x 2 Crosspoint Switch
Typical Operating Characteristics
(VCC = 3.3V, VCC_IN, VCC_OUT = 1.8V, VIN = 500mVP-P, TA = +25C, unless otherwise noted.)
MAX3841
CORE SUPPLY CURRENT vs. TEMPERATURE (EXCLUDES CML I/O CURRENTS)
MAX3841 toc01
SUPPLY CURRENT vs. TEMPERATURE (CORE PLUS CML I/O CURRENTS)
130 120 SUPPLY CURRENT (mA) 110 100 90 80 70 60 50 40 CML INPUTS AND OUTPUTS AC-COUPLED -40 -15 10 35 60 85 0 OUTPUTS ENABLE 60mV/div 2 OUTPUTS ENABLE 1 OUTPUT ENABLE
MAX3841 toc02
OUTPUT EYE DIAGRAM (12.5Gbps, 223 - 1 PRBS)
MAX3841 toc03
140 130 120 SUPPLY CURRENT (mA) 110 100 90 80 70 60 50 40 -40 -15 10 35 60 2 OUTPUTS ENABLE 0 OUTPUTS ENABLE 1 OUTPUT ENABLE
140
85
14ps/div
TEMPERATURE (C)
TEMPERATURE (C)
OUTPUT EYE DIAGRAM (10.7Gbps, 223 - 1 PRBS)
MAX3841 toc04
OUTPUT EYE DIAGRAM (6.25Gbps, 223 - 1 PRBS)
MAX3841 toc05
OUTPUT EYE DIAGRAM (622Mbps, 223 - 1 PRBS)
MAX3841 toc06
60mV/div
60mV/div
60mV/div
16ps/div
28ps/div
270ps/div
DETERMINISTIC JITTER vs. TEMPERATURE
14 DETERMINISTIC JITTER (ps) 12 10 8 6 4 2 0 -40 -15 10 35 60 85 TEMPERATURE (C) K28.5 AT 12.5Gbps 27 - 1 PRBS + 100CIDs AT 10.7Gbps
MAX3841 toc07
DIFFERENTIAL OUTPUT SWING vs. TEMPERATURE
540 DIFFERENTIAL OUTPUT (mVP-P) 530 520 510 500 490 480 470 460 450 -40 -15 10 35 60 85 OUT1
MAX3841 toc08
PROPAGATION DELAY
MAX3841 toc09
16
550
IN1
100ps/div
TEMPERATURE (C)
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12.5Gbps CML 2 x 2 Crosspoint Switch MAX3841
Pin Description
PIN 1, 12 2, 5 3 4 6 7 8, 11 9 10 13, 24 14, 17 15 16 18 19 20, 23 21 22 EP NAME VCC VCC1IN IN1+ IN1SEL1 SEL2 VCC2IN IN2+ IN2GND VCC1OUT OUT1OUT1+ ENO1 ENO2 VCC2OUT OUT2OUT2+ Exposed Pad +3.3V Core Supply Voltage Supply Voltage for CML Input IN1. Connect to 1.8V, 2.5V, or 3.3V. Positive Serial Data Input 1, CML Negative Serial Data Input 1, CML Output 1 Select, LVCMOS Input. See Table 1. Output 2 Select, LVCMOS Input. See Table 1. Supply Voltage for CML Input IN2. Connect to 1.8V, 2.5V, or 3.3V. Positive Serial Data Input 2, CML Negative Serial Data Input 2, CML Supply Ground Supply Voltage for CML Output OUT1. Connect to 1.8V, 2.5V, or 3.3V. Negative Serial Data Output 1, CML Positive Serial Data Output 1, CML Output 1 Enable, LVCMOS Input. See Table 1. Output 2 Enable, LVCMOS Input. See Table 1. Supply Voltage for CML Output OUT2. Connect to 1.8V, 2.5V, or 3.3V. Negative Serial Data Output 2, CML Positive Serial Data Output 2, CML Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. FUNCTION
Detailed Description
The MAX3841 contains a pair of CML inputs that drive two 2:1 multiplexers, with separate select inputs SEL1 and SEL2, providing a 2 x 2 crosspoint data path. The outputs of the multiplexers each drive a high-performance CML output that can be disabled (powered down) using the ENO1/ENO2 inputs. All of the data paths are fully differential to minimize jitter, crosstalk, and signal skew. See Figure 1 for the functional diagram.
The CML inputs accept serial NRZ data with differential amplitude from 150mVP-P to 1200mVP-P (see Figure 2). The CML outputs provide 500mVP-P nominal differential swing, resulting in low power consumption.
2 IN1 CML 1 CML 0 ENO1 2 IN2 CML 1 CML 0 ENO2 2 OUT2 SEL1 2 OUT1
CML Input and Output Buffers
The MAX3841 input and output buffers are terminated with 50 to independent supply lines, and are also compatible with 100 differential terminations. (See Figures 3 and 4.) Separate power-supply connections are provided for the core, input buffers, and output buffers to allow DCcoupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the CML inputs and outputs can be AC-coupled.
MAX3841
SEL2
Figure 1. Functional Diagram
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12.5Gbps CML 2 x 2 Crosspoint Switch MAX3841
V600mV MAX V+
Table 1. Output Controls
75mV MIN
ENO1 0 0 0 0 1
ENO2 0 0 0 0 1
SEL1 0 0 1 1 X
SEL2 0 1 0 1 X
OUT1 IN2 IN2 IN1 IN1 Disabled
OUT2 IN1 IN2 IN1 IN2 Disabled
150mV MIN (V+) - (V-) 1200mV MAX
Applications Information
Select and Enable Controls
The MAX3841 provides two LVCMOS-compatible select inputs, SEL1 and SEL2. Either data input can be connected to either or both data outputs. The MAX3841 provides two LVCMOS-compatible enable inputs, ENO1 and ENO2, so each output can be disabled independently. The MAX3841 can also be used as a 1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using the LVCMOS control inputs accordingly (see Table 1).
Figure 2. Definition of Differential Voltage Swing
VCC_IN
50 IN_+
50
Power-Supply Connections
Each of the input and output power-supply connections (VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is independent and need not be connected to the same voltage. The input and output supplies can be connected to 1.8V, 2.5V, or 3.3V, but the core supply (VCC) must be connected to 3.3V for proper operation.
IN_-
MAX3841
Input and Output Interfaces
Figure 3. Equivalent CML Input Circuit
VCC_OUT
50
50 OUT_+ OUT_-
The MAX3841 inputs and outputs can be AC-coupled or DC-coupled according to the application. If an input or output is not used it should be terminated with 50 to the correct input or output supply voltage. For more information about interfacing with logic families, refer to Maxim application note HFAN-01.0: Introduction to LVDS, PECL, and CML. The MAX3841 is packaged in a 4mm x 4mm 24-pin thin QFN with exposed pad. The exposed pad provides thermal and electrical connectivity to the IC and must be soldered to a high-frequency ground plane. Use multiple vias to connect the exposed pad underneath the package to the PC board ground plane. Use good layout techniques for the 10Gbps PC board transmission lines, and configure the layout near the IC to minimize impedance discontinuities. Power-supply decoupling capacitors should be located as close as possible to the IC.
Package and Layout Considerations
MAX3841
Figure 4. Equivalent CML Output Circuit _______________________________________________________________________________________ 5
12.5Gbps CML 2 x 2 Crosspoint Switch MAX3841
Pin Configuration
VCC2OUT OUT2+ OUT2TOP VIEW GND VCC2OUT
Chip Information
TRANSISTOR COUNT: 950 PROCESS: SiGe BiCMOS
24 23 22 21 20 19 VCC VCC1IN IN1+ IN1VCC1IN SEL1 1 2 3 4 5 6 7 SEL2 8 VCC2IN 9 IN2+ 10 11 12 IN2VCC2IN VCC 18 ENO1 17 VCC1OUT 16 OUT1+
MAX3841
ENO2 15 OUT114 VCC1OUT 13 GND
THIN QFN* *THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION.
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12.5Gbps CML 2 x 2 Crosspoint Switch
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
MAX3841
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
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12.5Gbps CML 2 x 2 Crosspoint Switch MAX3841
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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